# -*- coding: UTF-8 -*-

import os
import shutil

"""
将example里需要使用的文件copy到指定目录

注意设置文件路径
"""

import argparse
parser = argparse.ArgumentParser(description="copy IP files to user project")
parser.add_argument("--src", help="IP files")
parser.add_argument("--dest", help='user project')
args = parser.parse_args()

# 最后需要带路径分隔符
# SRC_PATH = 'D:/tmp/vivado/mac_core_ex/imports/'
# DEST_PATH = "../hdl/imports/"
SRC_PATH = args.src
DEST_PATH = args.dest

IP_NAME = 'mac_core'

if os.path.isdir(DEST_PATH):
    pass
else:
    os.mkdir(DEST_PATH)

shutil.copyfile(SRC_PATH + IP_NAME + '_bram_tdp.v',                 DEST_PATH + IP_NAME + '_bram_tdp.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_config_vector_sm.v',         DEST_PATH + IP_NAME + '_config_vector_sm.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_example_design_resets.v',    DEST_PATH + IP_NAME + '_example_design_resets.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_example_design.v',           DEST_PATH + IP_NAME + '_example_design.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_fifo_block.v',               DEST_PATH + IP_NAME + '_fifo_block.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_reset_sync.v',               DEST_PATH + IP_NAME + '_reset_sync.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_rx_client_fifo.v',           DEST_PATH + IP_NAME + '_rx_client_fifo.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_support.v',                  DEST_PATH + IP_NAME + '_support.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_support_resets.v',           DEST_PATH + IP_NAME + '_support_resets.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_sync_block.v',               DEST_PATH + IP_NAME + '_sync_block.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_ten_100_1g_eth_fifo.v',      DEST_PATH + IP_NAME + '_ten_100_1g_eth_fifo.v')
shutil.copyfile(SRC_PATH + IP_NAME + '_tx_client_fifo.v',           DEST_PATH + IP_NAME + '_tx_client_fifo.v')


"""
修改顶层文件
"""
old_file_name = DEST_PATH + IP_NAME + '_example_design.v'
new_file_name = DEST_PATH + IP_NAME + '_user_top.v'

old_file = open(old_file_name, 'r')
new_file = open(new_file_name, 'w')

comment_module = False
for each_line in old_file.readlines():
    if each_line.find('output        phy_resetn') != -1:     #
        new_file.write(each_line)
        new_file.write('\n')
        new_file.write('\tinput   wire                  refclk_bufg,\n')
        new_file.write('\tinput   wire                  gtx_clk_bufg,\n')
        new_file.write('\n')
        new_file.write('\t input   wire                  tx_fifo_clock,\n')
        new_file.write('\tinput   wire                  tx_axis_fifo_tvalid,\n')
        new_file.write('\tinput   wire  [7:0]           tx_axis_fifo_tdata,\n')
        new_file.write('\tinput   wire                  tx_axis_fifo_tlast,\n')
        new_file.write('\toutput  wire                  tx_axis_fifo_tready,\n')
        new_file.write('\n')
        new_file.write('\tinput  wire                   rx_fifo_clock,\n')
        new_file.write('\toutput wire  [7:0]            rx_axis_fifo_tdata,\n')
        new_file.write('\toutput wire                   rx_axis_fifo_tvalid,\n')
        new_file.write('\toutput wire                   rx_axis_fifo_tlast,\n')
        new_file.write('\tinput  wire                   rx_axis_fifo_tready,\n')
        new_file.write('\n')

    elif each_line.find('module ' + IP_NAME + '_example_design') != -1:
        new_file.write('module ' + IP_NAME + '_user_top\n')

    elif each_line.find('input         clk_in_p') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('input         clk_in_n,') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 gtx_clk_bufg;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 refclk_bufg;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 rx_fifo_clock;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire  [7:0]          rx_axis_fifo_tdata;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 rx_axis_fifo_tvalid;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 rx_axis_fifo_tready;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 rx_axis_fifo_tlast;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 tx_fifo_clock;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire  [7:0]          tx_axis_fifo_tdata;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 tx_axis_fifo_tvalid;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 tx_axis_fifo_tlast;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('wire                 tx_axis_fifo_tready;') != -1:
        new_file.write('//' + each_line)

    elif each_line.find('assign tx_fifo_clock = gtx_clk_bufg;') != -1:
        new_file.write('//' + each_line)
    elif each_line.find('assign rx_fifo_clock = gtx_clk_bufg;') != -1:
        new_file.write('//' + each_line)

    elif each_line.find('.s_axi_aclk       (s_axi_aclk),') != -1:
        new_file.write('\t')
        new_file.write('.s_axi_aclk          (gtx_clk_bufg),')
        new_file.write('\n')

    elif each_line.find('endmodule') != -1:
        new_file.write('\t')
        new_file.write('assign                  dcm_locked = 1\'b1;')       # 非常重要的一句
        new_file.write('\n')
        new_file.write(each_line)

    # 注释例化代码
    elif each_line.find(IP_NAME + '_example_design_clocks') != -1:
        new_file.write('/*\n')
        new_file.write(each_line)
        comment_module = True
        continue

    elif each_line.find(IP_NAME + '_basic_pat_gen') != -1:
        new_file.write('/*\n')
        new_file.write(each_line)
        comment_module = True
        continue

    elif each_line.find(');') != -1 and comment_module:
        new_file.write(each_line)
        new_file.write('*/\n')
        comment_module = False
        continue
    else:
        new_file.write(each_line)

old_file.close()
new_file.close()
